1. Field of the Invention
The present invention relates to an address alignment system, and more particularly, to an address alignment system for a semiconductor memory device.
2. Discussion of the Related Art
Generally, a semiconductor memory device uses memory elements and a decoder for selecting memory words, together with memory cells, designated by input addresses.
A conventional decoder for the semiconductor memory device will be discussed with reference to the attached drawings. FIG. 1 is a block diagram showing a conventional decoder system for a semiconductor memory device. The conventional semiconductor memory device includes "mxn" binary memory cells 2 for accommodating "m" words of "n" bits, and an address decoder 1 for selecting each word. Each binary memory cell is a basic design block of the semiconductor memory device.
Two address inputs are connected to the address decoder 1, which is operated by a memory enable signal. If the memory enable signal sent to the address decoder 1 is "0", the output of the address decoder 1 becomes "0" so that no word can be selected. If a memory enable signal sent to the address decoder 1 is "1", one of four words is selected according to the value of the two address inputs. In this case, if a reading/writing signal is "1", storage values of a binary memory cell 2 on designated words pass through three OR gates 3 and are produced through output ports. Since other binary memory cells 2 generate "0", they don't affect the output. If the reading/writing signal is "0", information standby at an input port is stored in a binary memory cell 2 on a designated word.
In the conventional semiconductor device, if the address decoder 1 receives an address, memory cells of many bytes on the designated row are simultaneously accessed.
The conventional semiconductor memory device has the following problems. It only provides accessibility to the memory cells on a designated row upon receiving an address in an address decoder. It cannot provide continuity in input of addresses. Therefore, if when storing data with lengths and addresses over two rows, since the semiconductor memory device operates in divided steps for each of the rows, the operation speed is very low.